<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>MPAMF_IDR</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">MPAMF_IDR, MPAM Features Identification Register</h1><p>The MPAMF_IDR characteristics are:</p><h2>Purpose</h2>
        <p>Indicates which memory partitioning and monitoring features are present on this MSC.</p>

      
        <p>MPAMF_IDR_s indicates the MPAM features accessed from the Secure MPAM feature page.
MPAMF_IDR_ns indicates the MPAM features accessed from the Non-secure MPAM feature page.
MPAMF_IDR_rt indicates the MPAM features accessed from the Root MPAM feature page.
MPAMF_IDR_rl indicates the MPAM features accessed from the Realm MPAM feature page.</p>

      
        <p>When MPAMF_IDR.HAS_RIS is 1, some fields in this register give information for the resource instance selected by <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS. The description of every field that is affected by <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS has that information within the field description.</p>
      <h2>Configuration</h2><p>The power domain of MPAMF_IDR is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.
    </p><p>This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMF_IDR are <span class="arm-defined-word">RES0</span>.</p>
        <p>MPAMF_IDR is 64-bit register when MPAM v0.1 or v1.1 is implemented.</p>

      
        <p>Otherwise, MPAMF_IDR is a 32-bit register.</p>

      
        <p>The power and reset domain of each MSC component is specific to that component.</p>
      <h2>Attributes</h2>
        <p>MPAMF_IDR is a:</p>

      
        <ul>
<li>64-bit register when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented
</li><li>32-bit register otherwise
</li></ul>
      <h2>Field descriptions</h2><h3>When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented:</h3><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-63_60">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-59_56-1">RIS_MAX</a></td><td class="lr" colspan="12"><a href="#fieldset_0-55_44">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-43_43-1">HAS_NFU</a></td><td class="lr" colspan="1"><a href="#fieldset_0-42_42-1">HAS_ENDIS</a></td><td class="lr" colspan="1"><a href="#fieldset_0-41_41-1">SP4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-40_40-1">HAS_ERR_MSI</a></td><td class="lr" colspan="1"><a href="#fieldset_0-39_39-1">HAS_ESR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-38_38-1">HAS_EXTD_ESR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-37_37-1">NO_IMPL_MSMON</a></td><td class="lr" colspan="1"><a href="#fieldset_0-36_36-1">NO_IMPL_PART</a></td><td class="lr" colspan="3"><a href="#fieldset_0-35_33">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-32_32-1">HAS_RIS</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">HAS_PARTID_NRW</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_30">HAS_MSMON</a></td><td class="lr" colspan="1"><a href="#fieldset_0-29_29">HAS_IMPL_IDR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-28_28-1">EXT</a></td><td class="lr" colspan="1"><a href="#fieldset_0-27_27">HAS_PRI_PART</a></td><td class="lr" colspan="1"><a href="#fieldset_0-26_26">HAS_MBW_PART</a></td><td class="lr" colspan="1"><a href="#fieldset_0-25_25">HAS_CPOR_PART</a></td><td class="lr" colspan="1"><a href="#fieldset_0-24_24">HAS_CCAP_PART</a></td><td class="lr" colspan="8"><a href="#fieldset_0-23_16">PMG_MAX</a></td><td class="lr" colspan="16"><a href="#fieldset_0-15_0">PARTID_MAX</a></td></tr></tbody></table><h4 id="fieldset_0-63_60">Bits [63:60]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-59_56-1">RIS_MAX, bits [59:56]<span class="condition"><br/>When MPAMF_IDR.EXT == 1 and MPAMF_IDR.HAS_RIS == 1:
                        </span></h4><div class="field">
      <p>Maximum RIS value supported in <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>. Must be <span class="binarynumber">0b0000</span> if <a href="ext-mpamf_idr.html">MPAMF_IDR</a>.HAS_RIS == 0.</p>
    </div><h4 id="fieldset_0-59_56-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-55_44">Bits [55:44]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-43_43-1">HAS_NFU, bit [43]<span class="condition"><br/>When FEAT_MPAMv1p1 is implemented or FEAT_MPAMv0p1 is implemented:
                        </span></h4><div class="field">
      <p>Has No Future Use field in <a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a>. Indicates that <a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a>.NFU is implemented.</p>
    <table class="valuetable"><tr><th>HAS_NFU</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a>.NFU is not implemented. A PARTID disabled through access to MPAMCFG_DIS must preserve the control settings of the disabled PARTID.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Implements <a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a>.NFU. A PARTID disabled with NFU as 1 may have its control settings forgotten.</p>
        </td></tr></table><p>If <a href="ext-mpamf_idr.html">MPAMF_IDR</a>.HAS_ENDIS is <span class="binarynumber">0b0</span>, this field must also be <span class="binarynumber">0b0</span>.</p>
<p>This field must be the same in each instance of this register and for any value in <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS.</p></div><h4 id="fieldset_0-43_43-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-42_42-1">HAS_ENDIS, bit [42]<span class="condition"><br/>When FEAT_MPAMv1p1 is implemented or FEAT_MPAMv0p1 is implemented:
                        </span></h4><div class="field">
      <p>Has PARTID enable and disable. Indicates that this MSC supports PARTID disable and enable via <a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a>, <a href="ext-mpamcfg_en.html">MPAMCFG_EN</a> and <a href="ext-mpamcfg_en_flags.html">MPAMCFG_EN_FLAGS</a> registers.</p>
    <table class="valuetable"><tr><th>HAS_ENDIS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support PARTID enable and disable functionality, and <a href="ext-mpamcfg_en.html">MPAMCFG_EN</a>, <a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a> and MPAMCFG_EN_FLAGS registers are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Supports PARTID enable and disable through the <a href="ext-mpamcfg_en.html">MPAMCFG_EN</a>, <a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a> and MPAMCFG_EN_FLAGS registers.</p>
        </td></tr></table><p>All three registers must be implemented when this field is 1, <a href="ext-mpamcfg_en.html">MPAMCFG_EN</a>, <a href="ext-mpamcfg_dis.html">MPAMCFG_DIS</a>, and <a href="ext-mpamcfg_en_flags.html">MPAMCFG_EN_FLAGS</a>.</p>
<p>This field must be the same in each instance of this register and for any value in <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS.</p></div><h4 id="fieldset_0-42_42-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-41_41-1">SP4, bit [41]<span class="condition"><br/>When FEAT_RME is implemented:
                        </span></h4><div class="field">
      <p>Indicates whether this MSC supports 4 PARTID spaces.</p>
    <table class="valuetable"><tr><th>SP4</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>This MSC supports two PARTID spaces.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This MSC supports four PARTID spaces.</p>
        </td></tr></table>
      <p>This field must read the same in each instance of this register and for any value in <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS.</p>
    </div><h4 id="fieldset_0-41_41-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-40_40-1">HAS_ERR_MSI, bit [40]<span class="condition"><br/>When MPAMF_IDR.EXT == 1:
                        </span></h4><div class="field">
      <p>Has support for MSI writes to signal MPAM error interrupts. These registers are implemented: <a href="ext-mpamf_err_msi_addr_l.html">MPAMF_ERR_MSI_ADDR_L</a>, <a href="ext-mpamf_err_msi_addr_h.html">MPAMF_ERR_MSI_ADDR_H</a>, <a href="ext-mpamf_err_msi_attr.html">MPAMF_ERR_MSI_ATTR</a>, <a href="ext-mpamf_err_msi_data.html">MPAMF_ERR_MSI_DATA</a>, and <a href="ext-mpamf_err_msi_mpam.html">MPAMF_ERR_MSI_MPAM</a>.</p>
    <table class="valuetable"><tr><th>HAS_ERR_MSI</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-mpamf_err_msi_addr_l.html">MPAMF_ERR_MSI_ADDR_L</a>, <a href="ext-mpamf_err_msi_addr_h.html">MPAMF_ERR_MSI_ADDR_H</a>, <a href="ext-mpamf_err_msi_attr.html">MPAMF_ERR_MSI_ATTR</a>, <a href="ext-mpamf_err_msi_data.html">MPAMF_ERR_MSI_DATA</a>, and <a href="ext-mpamf_err_msi_mpam.html">MPAMF_ERR_MSI_MPAM</a> registers are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-mpamf_err_msi_addr_l.html">MPAMF_ERR_MSI_ADDR_L</a>, <a href="ext-mpamf_err_msi_addr_h.html">MPAMF_ERR_MSI_ADDR_H</a>, <a href="ext-mpamf_err_msi_attr.html">MPAMF_ERR_MSI_ATTR</a>, <a href="ext-mpamf_err_msi_data.html">MPAMF_ERR_MSI_DATA</a>, and <a href="ext-mpamf_err_msi_mpam.html">MPAMF_ERR_MSI_MPAM</a> are implemented and can be used to generate writes to signal error interrupts.</p>
        </td></tr></table>
      <p>If <a href="ext-mpamf_idr.html">MPAMF_IDR</a>.HAS_ESR is 0, this bit must also be 0.</p>
    </div><h4 id="fieldset_0-40_40-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-39_39-1">HAS_ESR, bit [39]<span class="condition"><br/>When MPAMF_IDR.EXT == 1:
                        </span></h4><div class="field">
      <p><a href="ext-mpamf_esr.html">MPAMF_ESR</a> is implemented.</p>
    <table class="valuetable"><tr><th>HAS_ESR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-mpamf_esr.html">MPAMF_ESR</a>, <a href="ext-mpamf_ecr.html">MPAMF_ECR</a>, and MPAM error handling are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-mpamf_esr.html">MPAMF_ESR</a>, <a href="ext-mpamf_ecr.html">MPAMF_ECR</a>, and MPAM error handling are implemented.</p>
        </td></tr></table>
      <p>If an MSC cannot encounter any of the error conditions listed in <span class="xref">'Errors in MSCs' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598)</span>, both the MPAMF_ESR and <a href="ext-mpamf_ecr.html">MPAMF_ECR</a> must be RAZ/WI.</p>
    </div><h4 id="fieldset_0-39_39-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-38_38-1">HAS_EXTD_ESR, bit [38]<span class="condition"><br/>When MPAMF_IDR.EXT == 1:
                        </span></h4><div class="field">
      <p><a href="ext-mpamf_esr.html">MPAMF_ESR</a> is 64 bits.</p>
    <table class="valuetable"><tr><th>HAS_EXTD_ESR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-mpamf_esr.html">MPAMF_ESR</a> is 32 bits.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-mpamf_esr.html">MPAMF_ESR</a> is 64 bits.</p>
        </td></tr></table>
      <p>When <a href="ext-mpamf_idr.html">MPAMF_IDR</a>.HAS_RIS and <a href="ext-mpamf_idr.html">MPAMF_IDR</a>.HAS_ESR, this field must be 1.</p>
    </div><h4 id="fieldset_0-38_38-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-37_37-1">NO_IMPL_MSMON, bit [37]<span class="condition"><br/>When MPAMF_IDR.EXT == 1 and MPAMF_IDR.HAS_IMPL_IDR == 1:
                        </span></h4><div class="field">
      <p><a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> defines no <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource monitors.</p>
    <table class="valuetable"><tr><th>NO_IMPL_MSMON</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> defines at least one <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource monitor.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> does not define any <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource monitors.</p>
        </td></tr></table>
      <p>If RIS is implemented, this field indicates the presence of <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource monitors described in <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> for the selected resource instance.</p>
    </div><h4 id="fieldset_0-37_37-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-36_36-1">NO_IMPL_PART, bit [36]<span class="condition"><br/>When MPAMF_IDR.EXT == 1 and MPAMF_IDR.HAS_IMPL_IDR == 1:
                        </span></h4><div class="field">
      <p><a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> defines no <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource controls.</p>
    <table class="valuetable"><tr><th>NO_IMPL_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> defines at least one <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource control.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> does not define any <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource controls.</p>
        </td></tr></table>
      <p>If RIS is implemented, this field indicates the presence of <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> resource controls described in <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a> for the selected resource instance.</p>
    </div><h4 id="fieldset_0-36_36-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-35_33">Bits [35:33]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-32_32-1">HAS_RIS, bit [32]<span class="condition"><br/>When MPAMF_IDR.EXT == 1:
                        </span></h4><div class="field">
      <p>Has resource instance selector. Indicates that <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a> contains the RIS field that selects a resource instance to control.</p>
    <table class="valuetable"><tr><th>HAS_RIS</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a> does not implement the <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS field or multiple resource instance support.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a> implements the <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS field and MPAM resource instance numbers up to and including MPAMF_IDR.RIS_MAX.</p>
        </td></tr></table></div><h4 id="fieldset_0-32_32-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_31">HAS_PARTID_NRW, bit [31]</h4><div class="field">
      <p>Has PARTID narrowing.</p>
    <table class="valuetable"><tr><th>HAS_PARTID_NRW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not have <a href="ext-mpamf_partid_nrw_idr.html">MPAMF_PARTID_NRW_IDR</a>, <a href="ext-mpamcfg_intpartid.html">MPAMCFG_INTPARTID</a>, or intPARTID mapping support.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Supports the <a href="ext-mpamf_partid_nrw_idr.html">MPAMF_PARTID_NRW_IDR</a>, <a href="ext-mpamcfg_intpartid.html">MPAMCFG_INTPARTID</a> registers.</p>
        </td></tr></table></div><h4 id="fieldset_0-30_30">HAS_MSMON, bit [30]</h4><div class="field">
      <p>Has resource Monitors. Indicates whether this MSC has MPAM resource monitors.</p>
    <table class="valuetable"><tr><th>HAS_MSMON</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support MPAM resource monitoring by groups or <a href="ext-mpamf_msmon_idr.html">MPAMF_MSMON_IDR</a>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Supports resource monitoring by matching a combination of PARTID and PMG. See <a href="ext-mpamf_msmon_idr.html">MPAMF_MSMON_IDR</a>.</p>
        </td></tr></table></div><h4 id="fieldset_0-29_29">HAS_IMPL_IDR, bit [29]</h4><div class="field">
      <p>Has <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>. Indicates whether this MSC has the <span class="arm-defined-word">IMPLEMENTATION SPECIFIC</span> MPAM features register, <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>.</p>
    <table class="valuetable"><tr><th>HAS_IMPL_IDR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not have <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>.</p>
        </td></tr></table></div><h4 id="fieldset_0-28_28-1">EXT, bit [28]<span class="condition"><br/>When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented:
                        </span></h4><div class="field">
      <p>Extended MPAMF_IDR.</p>
    <table class="valuetable"><tr><th>EXT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>MPAMF_IDR has no defined bits in [63:32]. The register is effectively 32 bits.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>MPAMF_IDR has bits defined in [63:32]. The register is 64-bits.</p>
        </td></tr></table></div><h4 id="fieldset_0-28_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-27_27">HAS_PRI_PART, bit [27]</h4><div class="field">
      <p>Has Priority Partitioning. Indicates that MPAM priority partitioning is implemented and <a href="ext-mpamf_pri_idr.html">MPAMF_PRI_IDR</a> exists.</p>
    <table class="valuetable"><tr><th>HAS_PRI_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support priority partitioning or have <a href="ext-mpamf_pri_idr.html">MPAMF_PRI_IDR</a>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has priority partitioning and <a href="ext-mpamf_pri_idr.html">MPAMF_PRI_IDR</a>.</p>
        </td></tr></table>
      <p>If RIS is implemented, this field indicates the presence of priority partitioning resource controls as described in <a href="ext-mpamf_pri_idr.html">MPAMF_PRI_IDR</a> for the selected resource instance.</p>
    </div><h4 id="fieldset_0-26_26">HAS_MBW_PART, bit [26]</h4><div class="field">
      <p>Has Memory Bandwidth Partitioning. Indicates whether this MSC implements MPAM memory bandwidth partitioning and <a href="ext-mpamf_mbw_idr.html">MPAMF_MBW_IDR</a>.</p>
    <table class="valuetable"><tr><th>HAS_MBW_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support memory bandwidth partitioning or have <a href="ext-mpamf_mbw_idr.html">MPAMF_MBW_IDR</a> register.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_mbw_idr.html">MPAMF_MBW_IDR</a> register.</p>
        </td></tr></table>
      <p>If RIS is implemented, this field indicates the presence of memory bandwidth partitioning resource controls as described in <a href="ext-mpamf_mbw_idr.html">MPAMF_MBW_IDR</a> for the selected resource instance.</p>
    </div><h4 id="fieldset_0-25_25">HAS_CPOR_PART, bit [25]</h4><div class="field">
      <p>Has Cache Portion Partitioning. Indicates whether this MSC implements MPAM cache portion partitioning and <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a>.</p>
    <table class="valuetable"><tr><th>HAS_CPOR_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support cache portion partitioning or have <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a> or <a href="ext-mpamcfg_cpbmn.html">MPAMCFG_CPBM&lt;n&gt;</a> registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a> and <a href="ext-mpamcfg_cpbmn.html">MPAMCFG_CPBM&lt;n&gt;</a> registers.</p>
        </td></tr></table>
      <p>If RIS is implemented, this field indicates the presence of cache portion partitioning resource controls as described in <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a> for the selected resource instance.</p>
    </div><h4 id="fieldset_0-24_24">HAS_CCAP_PART, bit [24]</h4><div class="field">
      <p>Has Cache Capacity Partitioning. Indicates whether this MSC implements MPAM cache capacity partitioning and the <a href="ext-mpamf_ccap_idr.html">MPAMF_CCAP_IDR</a> and <a href="ext-mpamcfg_cmax.html">MPAMCFG_CMAX</a> registers.</p>
    <table class="valuetable"><tr><th>HAS_CCAP_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support cache capacity partitioning or have <a href="ext-mpamf_ccap_idr.html">MPAMF_CCAP_IDR</a> and <a href="ext-mpamcfg_cmax.html">MPAMCFG_CMAX</a> registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_ccap_idr.html">MPAMF_CCAP_IDR</a> and <a href="ext-mpamcfg_cmax.html">MPAMCFG_CMAX</a> registers.</p>
        </td></tr></table>
      <p>If RIS is implemented, this field indicates the presence of cache capacity partitioning resource controls as described in <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a> for the selected resource instance.</p>
    </div><h4 id="fieldset_0-23_16">PMG_MAX, bits [23:16]</h4><div class="field">
      <p>Maximum supported value of PMG.</p>
    <p>The value of this field is permitted to vary between the instances of <a href="ext-mpamf_idr.html">MPAMF_IDR</a>, each reporting the maximum supported PMG value in the  PARTID space associated with that instance.</p>
<p>In MPAMF_IDR_s, this field is permitted to report the maximum PMG value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PMG value for the Secure PARTID space can be read from <a href="ext-mpamf_sidr.html">MPAMF_SIDR</a>.PMG_MAX.</p></div><h4 id="fieldset_0-15_0">PARTID_MAX, bits [15:0]</h4><div class="field">
      <p>Maximum supported value of PARTID.</p>
    <p>The value of this field is permitted to vary between the instances of <a href="ext-mpamf_idr.html">MPAMF_IDR</a>, each reporting the maximum supported PARTID value in the  PARTID space associated with that instance.</p>
<p>In MPAMF_IDR_s, this field is permitted to report the maximum PARTID value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PARTID value for the Secure PARTID space can be read from <a href="ext-mpamf_sidr.html">MPAMF_SIDR</a>.PARTID_MAX.</p></div><h3>Otherwise:</h3><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_1-31_31">HAS_PARTID_NRW</a></td><td class="lr" colspan="1"><a href="#fieldset_1-30_30">HAS_MSMON</a></td><td class="lr" colspan="1"><a href="#fieldset_1-29_29">HAS_IMPL_IDR</a></td><td class="lr" colspan="1"><a href="#fieldset_1-28_28-1">EXT</a></td><td class="lr" colspan="1"><a href="#fieldset_1-27_27">HAS_PRI_PART</a></td><td class="lr" colspan="1"><a href="#fieldset_1-26_26">HAS_MBW_PART</a></td><td class="lr" colspan="1"><a href="#fieldset_1-25_25">HAS_CPOR_PART</a></td><td class="lr" colspan="1"><a href="#fieldset_1-24_24">HAS_CCAP_PART</a></td><td class="lr" colspan="8"><a href="#fieldset_1-23_16">PMG_MAX</a></td><td class="lr" colspan="16"><a href="#fieldset_1-15_0">PARTID_MAX</a></td></tr></tbody></table><h4 id="fieldset_1-31_31">HAS_PARTID_NRW, bit [31]</h4><div class="field">
      <p>Has PARTID Narrowing.</p>
    <table class="valuetable"><tr><th>HAS_PARTID_NRW</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not have <a href="ext-mpamf_partid_nrw_idr.html">MPAMF_PARTID_NRW_IDR</a>, <a href="ext-mpamcfg_intpartid.html">MPAMCFG_INTPARTID</a>, or intPARTID mapping support.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Supports the <a href="ext-mpamf_partid_nrw_idr.html">MPAMF_PARTID_NRW_IDR</a>, <a href="ext-mpamcfg_intpartid.html">MPAMCFG_INTPARTID</a> registers.</p>
        </td></tr></table></div><h4 id="fieldset_1-30_30">HAS_MSMON, bit [30]</h4><div class="field">
      <p>Has resource Monitors. Indicates whether this MSC has MPAM resource monitors.</p>
    <table class="valuetable"><tr><th>HAS_MSMON</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support MPAM resource monitoring by groups or <a href="ext-mpamf_msmon_idr.html">MPAMF_MSMON_IDR</a>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Supports resource monitoring by matching a combination of PARTID and PMG. See <a href="ext-mpamf_msmon_idr.html">MPAMF_MSMON_IDR</a>.</p>
        </td></tr></table></div><h4 id="fieldset_1-29_29">HAS_IMPL_IDR, bit [29]</h4><div class="field">
      <p>Has <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>. Indicates whether this MSC has the <span class="arm-defined-word">IMPLEMENTATION SPECIFIC</span> MPAM features register, <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>.</p>
    <table class="valuetable"><tr><th>HAS_IMPL_IDR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not have <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_impl_idr.html">MPAMF_IMPL_IDR</a>.</p>
        </td></tr></table></div><h4 id="fieldset_1-28_28-1">EXT, bit [28]<span class="condition"><br/>When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented:
                        </span></h4><div class="field">
      <p>Extended MPAMF_IDR.</p>
    <table class="valuetable"><tr><th>EXT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>MPAMF_IDR has no defined bits in [63:32]. The register is effectively 32 bits.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>MPAMF_IDR has bits defined in [63:32]. The register is 64-bits.</p>
        </td></tr></table></div><h4 id="fieldset_1-28_28-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_1-27_27">HAS_PRI_PART, bit [27]</h4><div class="field">
      <p>Has Priority Partitioning. Indicates whether this MSC implements MPAM priority partitioning and <a href="ext-mpamf_pri_idr.html">MPAMF_PRI_IDR</a>.</p>
    <table class="valuetable"><tr><th>HAS_PRI_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support priority partitioning or have <a href="ext-mpamf_pri_idr.html">MPAMF_PRI_IDR</a>.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_pri_idr.html">MPAMF_PRI_IDR</a>.</p>
        </td></tr></table></div><h4 id="fieldset_1-26_26">HAS_MBW_PART, bit [26]</h4><div class="field">
      <p>Has Memory Bandwidth Partitioning. Indicates whether this MSC implements MPAM memory bandwidth partitioning and MPAMF_MBW_IDR.</p>
    <table class="valuetable"><tr><th>HAS_MBW_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support memory bandwidth partitioning or have <a href="ext-mpamf_mbw_idr.html">MPAMF_MBW_IDR</a> register.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_mbw_idr.html">MPAMF_MBW_IDR</a> register.</p>
        </td></tr></table></div><h4 id="fieldset_1-25_25">HAS_CPOR_PART, bit [25]</h4><div class="field">
      <p>Has Cache Portion Partitioning. Indicates whether this MSC implements MPAM cache portion partitioning and <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a>.</p>
    <table class="valuetable"><tr><th>HAS_CPOR_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support cache portion partitioning or have <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a> or <a href="ext-mpamcfg_cpbmn.html">MPAMCFG_CPBM&lt;n&gt;</a> registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_cpor_idr.html">MPAMF_CPOR_IDR</a> and <a href="ext-mpamcfg_cpbmn.html">MPAMCFG_CPBM&lt;n&gt;</a> registers.</p>
        </td></tr></table></div><h4 id="fieldset_1-24_24">HAS_CCAP_PART, bit [24]</h4><div class="field">
      <p>Has Cache Capacity Partitioning. Indicates whether this MSC implements MPAM cache capacity partitioning and the MPAMF_CCAP_IDR and MPAMCFG_CMAX registers.</p>
    <table class="valuetable"><tr><th>HAS_CCAP_PART</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Does not support cache capacity partitioning or have <a href="ext-mpamf_ccap_idr.html">MPAMF_CCAP_IDR</a> and <a href="ext-mpamcfg_cmax.html">MPAMCFG_CMAX</a> registers.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Has <a href="ext-mpamf_ccap_idr.html">MPAMF_CCAP_IDR</a> and <a href="ext-mpamcfg_cmax.html">MPAMCFG_CMAX</a> registers.</p>
        </td></tr></table></div><h4 id="fieldset_1-23_16">PMG_MAX, bits [23:16]</h4><div class="field">
      <p>Maximum supported value of PMG.</p>
    <p>The value of this field is permitted to vary between the instances of <a href="ext-mpamf_idr.html">MPAMF_IDR</a>, each reporting the maximum supported PMG value in the  PARTID space associated with that instance.</p>
<p>In MPAMF_IDR_s this field is permitted to report the maximum PMG value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PMG value for the Secure PARTID space can be read from <a href="ext-mpamf_sidr.html">MPAMF_SIDR</a>.PMG_MAX.</p></div><h4 id="fieldset_1-15_0">PARTID_MAX, bits [15:0]</h4><div class="field">
      <p>Maximum supported value of PARTID.</p>
    <p>The value of this field is permitted to vary between the instances of <a href="ext-mpamf_idr.html">MPAMF_IDR</a>, each reporting the maximum supported PARTID value in the  PARTID space associated with that instance.</p>
<p>In MPAMF_IDR_s this field is permitted to report the maximum PARTID value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PARTID value for the Secure PARTID space can be read from <a href="ext-mpamf_sidr.html">MPAMF_SIDR</a>.PARTID_MAX.</p></div><h2>Accessing MPAMF_IDR</h2>
        <p>This register is within the MPAM feature page memory frames. In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps.</p>

      
        <p>MPAMF_IDR is read-only.</p>

      
        <p>MPAMF_IDR must be readable from the Non-secure, Secure, Root, and Realm MPAM feature pages.</p>

      
        <p>MPAMF_IDR is permitted to have the same contents when read from the Secure, Non-secure, Root, and Realm MPAM feature pages unless the register contents are different for the different versions:</p>

      
        <ul>
<li>MPAMF_IDR_s is permitted to have either the same or different contents to MPAMF_IDR_ns, MPAMF_IDR_rt, or MPAMF_IDR_rl.
</li><li>MPAMF_IDR_ns is permitted to have either the same or different contents to MPAMF_IDR_rt or MPAMF_IDR_rl.
</li><li>MPAMF_IDR_rt is permitted to have either the same or different contents to MPAMF_IDR_rl.
</li></ul>

      
        <p>There must be separate registers in the Secure (MPAMF_IDR_s), Non-secure (MPAMF_IDR_ns), Root (MPAMF_IDR_rt), and Realm (MPAMF_IDR_rl) MPAM feature pages.</p>

      
        <p>When <a href="ext-mpamf_idr.html">MPAMF_IDR</a>.HAS_RIS is 1, MPAMF_IDR shows the configuration of MSC MPAM for the  resource instance selected by <a href="ext-mpamcfg_part_sel.html">MPAMCFG_PART_SEL</a>.RIS. Fields that mention RIS in their field descriptions have values that track the implemented properties of the resource instance. Fields that do not mention RIS are constant across all resource instances.</p>
      <h4>MPAMF_IDR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_s</td><td><span class="hexnumber">0x0000</span></td><td>MPAMF_IDR_s</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_ns</td><td><span class="hexnumber">0x0000</span></td><td>MPAMF_IDR_ns</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_rt</td><td><span class="hexnumber">0x0000</span></td><td>MPAMF_IDR_rt</td></tr></table><p>When FEAT_RME is implemented, accesses on this interface are <span class="access_level">RO</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_rl</td><td><span class="hexnumber">0x0000</span></td><td>MPAMF_IDR_rl</td></tr></table><p>When FEAT_RME is implemented, accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
